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2 edition of Latch-up and radiation integrated circuit -- LURIC found in the catalog.

Latch-up and radiation integrated circuit -- LURIC

Donald B Estreich

Latch-up and radiation integrated circuit -- LURIC

a test chip for CMOS latch-up investigation

by Donald B Estreich

  • 310 Want to read
  • 36 Currently reading

Published by Dept. of Energy, Sandia Laboratories, for sale by the National Technical Information Service] in Albuquerque, N.M, [Springfield, Va .
Written in English

    Subjects:
  • Integrated circuits -- Testing

  • Edition Notes

    StatementDonald B. Estreich, Computer-Aided Design Division 2113, Sandia Laboratories ; prepared by Sandia Laboratories for the United States Department of Energy
    SeriesSAND ; 78-1540
    ContributionsUnited States. Dept. of Energy, Sandia Laboratories, Sandia Laboratories. Computer-Aided Design Division 2113
    The Physical Object
    Pagination74 p. :
    Number of Pages74
    ID Numbers
    Open LibraryOL17965143M


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Latch-up and radiation integrated circuit -- LURIC by Donald B Estreich Download PDF EPUB FB2

@article{osti_, title = {Latch-up and radiation integrated circuit--LURIC: a test chip for CMOS latch-up investigation}, author = {Estreich, D.B.}, Latch-up and radiation integrated circuit -- LURIC book = {A CMOS integrated circuit test chip (Latch-Up and Radiation Integrated Circuit--LURIC) designed for CMOS latch-up and radiation effects research is described.

The purpose of LURIC is (a) to provide information on the physics. Get this from a library. Latch-up and radiation integrated circuit -- LURIC: a test chip for CMOS latch-up investigation. [Donald B Estreich; United States. Department of Energy.; Sandia Laboratories.; Sandia Laboratories.

Computer-Aided Design Division ]. A CMOS integrated circuit test chip (Latch-Up and Radiation Integrated Circuit--LURIC) designed for CMOS latch-up and radiation effects research is described. the authors focused on Latch-up and radiation integrated circuit -- LURIC book of I.

Latch-Up, ESD, and Other Phenomena 3 2 Latch-Up Parasitic Latch-up and radiation integrated circuit -- LURIC book Isolation of the individual diodes, transistors, and capacitors from each other in an integrated circuit is achieved by reverse-biased P-N junctions.

During the development of the circuit, precautions are taken to ensure that these junctions always are reliably blocking File Size: KB. D.B. Estreich. Latchup and radiation integrated circuit (LURIC): a test chip for CMOS latchup investigation.

Sandia Laboratories Report SAND, Albuquerque, NM, November D.B. Estreich. The physics and modeling of latch-up and CMOS integrated circuits. Improve Latch-up Immunity by Circuit Solution Hui-Wen Tsai and Ming-Dou Ker Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan Abstract- A concept of active guard ring and its corresponding circuit solution to enhance the latch-up immunity of integrated circuits (IC) are proposed and verified in a um 5-V CMOS process.

A latch-up is a type of short circuit which can occur in an integrated circuit (IC). More specifically it is the inadvertent creation of a low-impedance path between the power supply rails of a MOSFET circuit, triggering a parasitic structure which disrupts proper functioning of the part, possibly even leading to its destruction due to overcurrent.A power cycle is required to correct this.

Redundant Circuits with Latch-up and radiation integrated circuit -- LURIC book Protection. (induced by the single event latch up) This paper presents new methods and design concepts to make application Latch-up and radiation integrated circuit -- LURIC book integrated circuit (ASIC.

capacitor, which limits the frequency that the circuit can be driven at due to the R x C value. This method works very well in DC op amp circuits, as op-amps draw very little peak current and the circuit is only amplifying DC; no AC component – no R x C problems.

CONCLUSION Latch-up in CMOS ICs is preventable. Simple circuitFile Size: KB. About the blog Adder AND ASIC Asynchronous Set Reset D Flip Flop Blocking Cache Cache Memory Characteristic curves Clock Divider CMOS Inverter CMOS Inverter Short Circuit Current DFF D Flip Flop DFT DIBL Difference Divide by 2 D Latch Equations Finite State Machine First Post Flip Flop Frequency Divider FSM Full Adder Hold Time Intro Inverter.

A CMOS integrated circuit test chip (Latch-Up and Radiation Integrated Circuit--LURIC) designed for CMOS latch-up and radiation effects research is described.

The purpose of LURIC is (a) to provide information on the physics of CMOS latch-up, (b) to study the layout dependence of CMOS latch-up, and (c) to provide special latch-up test. Abstract. This paper presents experimental results of transient gamma irradiation effects on two kinds of circuits.

One is a two-stage circuit consisting of a bipolar power device LCV and a bulk complementary metal-oxide-semiconductor (CMOS) device IDT, the other is a two-stage circuit consisting of a bipolar power device LCV and the equivalent circuit of the parasitic P-N-P-N Cited by: 6.

Transient-Induced Latchup in CMOS Integrated Circuits The book all semiconductor device engineers must read to gain a practical feel for latchup-induced failure to produce lower-cost and higher-density chips.

Ming-Dou Ker, National Chiao-Tung University, Taiwan Sheng-Fu Hsu, National Chiao-Tung University, Taiwan. Radiation Tests of Latchup Mitigation Circuits (New – One Year) Rada Description: Radiation effects on microelectronics are an important reliability issue for many space applications.

In particular, SEL susceptibility is often considered sufficient reason to not to use a device in space. Developing a Transient Induced Latch-up Standard for Testing Integrated Circuits and P-type) transistors on an integrated circuit can often result in current paths parallel to a desired functional circuit.

Latch-up (LU) occurs from the activation of four-layer pnpn structures (thyristors)File Size: KB. Latch-up is a failure mechanism of CMOS integrated cir-cuits characterized by excessive current drain coupled with Basic P-Substrate CMOS Inverter Cross Section with Latch-Up Circuit Model WHAT TO DO As might be expected, latch-up is highly dependent on the noisy supplies and radiation incidence can also contribute to or cause latch-up File Size: 52KB.

Latchup in CMOS Technology: The Problem and Its Cure (The Springer International Series in Engineering and Computer Science) [Troutman, R.R.] on *FREE* shipping on qualifying offers. Latchup in CMOS Technology: The Problem and Its Cure (The Springer International Series in Engineering and Computer Science)Brand: Springer.

Latch-up in a CMOS integrated circuit, causes unintended currents will possibly resulting with the destruction of the entire circuit, thus, it must be prevented. Explanation of the phenomena Figure 1 shows the cross section of a two-transistor CMOS integrated circuit where the nMOS is on the left hand side and the pMOS on the right hand side.

What is LATCH-UP More specifically it is the inadvertent creation of a low-impedance path between the power supply rails of a MOSFET circuit, triggering a parasitic structure which disrupts proper functioning of the part and possibly even leading to its destruction due to over-current.

A power cycle is required to correct this situation. Why a book on Iatchup. Latchup has been, and continues to be, a potentially serious CMOS reliability concern. This concern is becoming more widespread with the ascendency of CMOS as the dominant VLSI technology, particularly as parasitic bipolar characteristics continue to improve at ever smaller dimensions on silicon wafers with ever lower defect densities.

Latchup in Integrated Circuits from Energetic Protons † A. Johnston, G. Swift, and L. Edmonds Jet Propulsion Laboratory California Institute of Technology Pasadena, California Abstract Proton latchup was investigated for several CMOS integrated circuits, including a modern microprocessor.

The. Ker is doing research in the area of CMOS reliability that goes beyond transient latch-up. This book is a collection of IEEE papers already published along with some new content. I found this book to be very handy the design of internal FETS for power management devices.5/5.

Microelectron. Reliab., Vol. 31, No. 2/3, pp./ + Printed in Great Britain. Pergamon Press pie ANALYSIS OF d.c. AND a.c. ANOMALOUS LATCH-UP EFFECTS IN COMMERCIAL CMOS INTEGRATED CIRCUITS ENRICO ZANONI,* PAOLO PAVAN,* GIORGIO SPIAZZI,* BRUNO BONATF~ and CLAUDIO CANALI* *Dip.

di Elettronica ed Informatica, Universitfi Author: Enrico Zanoni, Paolo Pavan, Giorgio Spiazzi, Bruno Bonati, Claudio Canali. Nuclear Instmments and Methods in Physics Research B37/38 () North-Holland, Amsterdam IMPROVEMENT OF CMOS LATCH-UP IMMUNITY USING A HIGH ENERGY IMPLANTED BURIED LAYER Hsiao-Yi LIN and Chiu H.

TING Components Research, Intel Corporation, Mission College Blvd., SC, Santa Clara, CAUSA In this CMOS latch-up study, we compared Cited by: Component-Level Measurement for Transient-Induced Latch-up in CMOS ICs Under System-Level ESD Considerations Ming-Dou Ker, SeniorMember,IEEE, and Sheng-Fu Hsu, StudentMember,IEEE Abstract—To accurately evaluate the immunity of CMOS ICs against transient-induced latch-up (TLU) under the system-level.

The CD is a very versatile IC with many uses as we saw in the previous lab activity. For example, a single CD can be used to make a chain of 3 inverters, an inverter plus two transmission gates, or other complex logic functions such as NAND and NOR gates. Inverters and transmission gates are particularly useful for building D type latches or Master/Slave flip-flops.

Latch-up is a particular problem in CMOS caused by the physical structure of the manufacturing process. First, however, know what a thyristor is (aka an SCR or silicon controlled rectifier): A thyristor has a feature called hysteresis which allows.

TSAI AND KER: LAYOUT CONSIDERATION AND CIRCUIT SOLUTION TO PREVENT EOS FAILURE Fig. Measured supply voltage and related current for the original design (without the modification) (a) before and (b) after the negative I-test applying at the PAD 1.

White Paper: Single Event Latchup Protection Of Integrated Circuits Source: Maxwell Technologies This paper reports the test results from the development of the single event latchup protection circuitry (referred to as Maxwell Technologies LPT(tm) technology) for several integrated circuits which are known to latchup at unacceptably low LET.

The test circuit consisted of a breadboard of each LPTTM circuit type, a de-lidded ADS (the target of the radiation), and a 16 bit digital to analog converter circuit which provided a composite monitor of the ADS parallel data output.

The status signal was used to trigger a digital storage scope set to capture. The enhanced latch-up capability of the proposed LTIGBT with a p+ diverter was obtained due to the holes in the current directly reaching the cathode via the p+ divert region and p+ cathode layer beneath the n+ cathode layer.

KW - Forward blocking voltage. KW - Latch-up. KW - p+ divert structure. KW - Power integrated circuit. KW - Turn-offAuthor: Ey Goo Kang, Seung Hyun Moon, Man Young Sung. Cable Discharge Event (CDE) has been the main cause which damages the Ethernet interface in field applications.

The transmission line pulsing (TLP) system has been the most popular method to observe electric characteristics of the device under human-body Cited by: 2.

In the result, the proposed ESD protection circuit has latch-up immunity and high robustness. These characteristics permit the proposed circuit to apply to power clamp circuit. Consequently, the proposed LIGBT-based ESD protection circuit with a latch-up immune characteristic can be applied to analog integrated circuits.

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